1. Field of the Invention
The present invention relates to a data processing apparatus, a control device and a data storage device.
2. Description of the Prior Art
One proposed structure of a control device controls a FeRAM (Ferroelectric Random Access Memory) as a cache memory or HDD to store data from a PC system (see, for example, Non-Patent Document 1). In the structure, the FeRAM is configured as a nonvolatile random access memory maintaining data stored therein when a power supply is stopped. In this device, data in the FeRAM is not regularly needed to be evacuated to HDD in preparation to an unexpected stop power supply. This arrangement enables to increase amount of data stored to FeRAM, and to increase cache hit ratio.    Non-patent document 1: Daisaburo Takahashi et al. “A 128 Mb ChainFeRAMTM and System Designs for HDD Application and Enhanced HDD Performance”, IEEE Asian Solid-State Circuits Conference, Nov. 16-18, 2009, Taipei, Taiwan.
In this prior art data processing apparatus, code length of error correcting code is set predetermined length, and error correction of data is performed using error correcting code having the predetermined length. There is an upper limit in number of bits that is correctable. When the errors more than the upper limit of number of bits that is correctable occurs, this errors cannot be corrected. One method for correcting more error is to use error correcting code having longer code length. In this case, the time for encoding or decoding data in the error correction circuit increases, and consumption power of the error correction circuit increases.